Infer fanout plane drops from copper pours - #2929
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July 30, 2026 21:25
This was referenced Jul 30, 2026
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Summary
fanoutPourNetMap<copperpour>components in the current or enclosing subcircuitfanoutRoutingLayersthrough as the solver's allowed signal escape layersWhy
Plane termination belongs to the board's copper intent. Users should be able to
write a normal source-only trace to
net.GNDornet.VCCand have fanout dropit to the matching pour layer without declaring a singleton
BusFanoutTermination.If a net is poured on multiple layers, core reports the ambiguity and asks for
an explicit
fanoutPourNetMap.Dependency
@tscircuit/props@0.0.599Main branch sync
v0.0.1552getSimpleRouteJsonFromCircuitJson.tspatch is reduced from 102 changed lines to 38Validation
bunx tsc --noEmitbun run build